The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Application No. 2001-16961 filed on Mar. 30, 2001, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a mask for a photolithography process and a method of fabricating the same, and more particularly to a mask for a photolithography process and a method for improving an auxiliary feature, such as an assisted bar, a scattering bar or an intensity leveling bar, which is formed at peripheries of isolated edges of features corresponding to each circuit element of an integrated circuit, so as to correct the optical proximity effect (OPE).
2. Description of the Related Art
As the design rule of devices and connecting wires integrated in a semiconductor chip is reduced, conventional lithography techniques using an ultraviolet ray do not prevent the distortion of a pattern formed on a wafer. That is, even though an I-line and a DUV (deep ultraviolet) ray have wavelengths of 248 nm, a minimum design rule thereof is 100 nm, such that distortion of the pattern is caused by diffraction and interruption of light during a semiconductor device manufacturing process. The distortion of the pattern becomes more serious as the minimum design rule is reduced. Accordingly, it is required to compensate for distortion of the pattern occurring during a photolithography process because of a limit-resolution.
In a photolithography process, a pattern of a photo mask is copied on a wafer through an optical lens. Since an optical system for projecting an image acts as a low-band filter, the image formed on the wafer is distorted as compared with an original shape. For instance, when a rectangular-shaped mask is used, a circular pattern is formed on the wafer since the light having high-frequency, that is, the light corresponding to edges of the rectangular-shaped mask, is not transmitted. When the mask pattern has a large size, a basic spatial frequency is lowered, so that light having relatively high frequency can be transmitted through the mask, whereby an image substantially identical to the original image can be formed on the wafer. However, when the pattern has a small size, the spatial frequency becomes high, so that the transmission rate of light is reduced, whereby serious distortion results.
Various types of lithography equipment have been developed to reduce distortion, but distortion still remains a problem. For this reason, there has been an attempt to change the design of the mask to compensate for the distortion of the pattern. For example, optical proximity correction (OPC) has been considered. According to optical proximity correction, the shape of the mask is pre-deformed considering the distortion of the pattern, so as to form a required image on the wafer.
Optical proximity correction can be achieved when adjacent features are interacted with each other in such a manner that a pattern-dependent alteration can be created. That is, lines, which are designed to have the same dimension and which are arranged in a layout such that they have different proximity with respect to other features, have different dimension from each other after the developing process has been finished. Accordingly, densely arranged lines are differently transcribed as compared with spaced lines. If line dimension is not constantly reproduced, serious problems occur in the integrated chip (IC).
U.S. Pat. No. 5,242,770 discloses a mask including additional lines referred to as scattering bars, assisted bars or intensity leveling bars for performing the function of adjusting an edge intensity gradient of an isolated edge in a mask pattern. The gradient of the isolated edge is adjusted such that the gradient of the isolated edge matches the edge intensity gradient of a densely packed edge, by means of the additional lines. As a result, the isolated feature is identically transcribed with respect to the densely packed feature, so that the optical proximity effect is greatly reduced.
U.S. Pat. No. 5,663,893 discloses a method for adding sub-lithographic correction features to all features in an original mask pattern. The original mask pattern is segmented and the correction features are formed in each segment. As a result, computer processings are carried out in a time and memory efficient manner.
U.S. Pat. No. 5,821,014 discloses a design rule of a scattering bar between features which are spaced by a predetermined intermediate distance as compared with isolated features and densely packed features. Accordingly, the proximity correction is possible with respect to the densely packed features.
U.S. Pat. No. 6,120,952 discloses a method for reducing the proximity effect by adjusting a dimension of a main feature with respect to a proximity correction feature, after defining a space between the main feature and the proximity correction feature. By adjusting the dimension of the main feature, an optimum feature dimension can be transcribed.
As mentioned above, techniques for correcting the proximity effect using auxiliary features in the form of bars are variously developed and used in the field. However, the design rule of the conventional bar-type auxiliary features has the following limitations: 1) isolated edges, in which features are spaced by a predetermined distance, have to be used; 2) auxiliary features have to be spaced by a predetermined distance from the isolated edges; and 3) auxiliary features have to be spaced by a predetermined distance from each other.
Accordingly, in view of the above noted limitations, the created auxiliary features can be adapted for simple patterns, such as rectangular pattern. However, when the auxiliary features are used for complex patterns, such as an oblique line pattern, a U-shaped pattern, an L-shaped pattern, a T-shaped pattern, and a cross line pattern, the auxiliary features are asymmetrically created, or relatively short auxiliary features are removed by periphery auxiliary features having relatively long lengths.
In addition, when the shape of patterns are complicated, the created patterns cannot be matched with the design rule. In extreme cases, the singularity inspection by means of a design rule checking (DRC) is impossible.
Also, as auxiliary features are added to an area in which a distance between patterns are small, a distance between adjacent patterns is smaller so that a pattern bridge or a kissing effect is generated, thereby lowering the resolution of the mask. In addition, since the auxiliary features are created as a bar shape with respect to each isolated edge, the number of auxiliary features is increased, so that data of the whole mask pattern is increased. The data of the bar-type auxiliary features are represented as 32 bit data in case of GDS (Graphic Data System) II format, so that data treating time is increased if the data of the whole data set is increased. Also, it is difficult to inspect the mask and a great amount of memory capacitances are required.
Recently, a memory article such as a DRAM requires an integration degree above a GIGA level. Therefore, in order to integrate a great amount of memory cells in a limited area, a cell layout has a complex structure including a bending section instead of a straight section. In the case of a gate electrode pattern, an L-shaped cell layout is adopted so as to increase the current driving capacitance in a narrow area.
In the above gate electrode pattern, the entire length of a gate has to be uniformly formed in an active area. If the length of the gate is short, a critical value of the threshold voltage is extremely lowered by a short channel effect of a MOS FET, so that the cell malfunctions. In contrast, if the length of the gate is long, the current driving capacitance is reduced so that a critical operating speed is lowered.
In addition, in order to allow the MOS FETs to have the same features over the entire area of the chip, the length of the gates have to be uniformly maintained over the entire area of the chip. Accordingly, it is required to solve and improve the problem of the conventional auxiliary feature-creating algorithm.
The present invention is therefore directed to a mask, and a method of fabricating a mask, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
The present invention has been made to solve the above problems of the related art, and therefore has as an object to provide a mask capable of reducing the amount of data required by reducing the number of auxiliary features, wherein the auxiliary features corresponding to recessed corners are formed in a polygonal shape while maintaining the symmetry of the auxiliary features. Another object of the present invention is to provide a method for fabricating such a mask.
To achieve these and other objects of the present invention, there is provided a mask for optically transcribing a pattern corresponding to integrated circuits onto a semiconductor substrate, by using an exposure device. The mask has a plurality of features corresponding to circuit elements for forming the integrated circuits, and includes at least one recessed corner defined by two edges.
In addition, the mask has a plurality of polygonal proximity correcting auxiliary features including two extension parts which extend in parallel along each of two edges defining the recessed corner and that are spaced apart from the two edges by a predetermined distance. The two extension parts are bent at a same angle corresponding to the recessed corner, so as to be connected to each other. The proximity correcting auxiliary features have polygonal shapes with predetermined widths.
To also achieve the objects of the present invention, there is provided a method of fabricating a mask for optically transcribing a pattern corresponding to integrated circuits onto a semiconductor substrate, by using an exposure device. The method includes fabricating a plurality of features corresponding to circuit elements for forming integrated circuits onto the mask and including at least one recessed corner defined by two edges; and fabricating a plurality of polygonal proximity correcting auxiliary features having predetermined widths onto the mask, including two extension parts which extend in parallel along each of two edges defining the recessed corner and that are spaced apart from the two edges by a predetermined distance. The two extension parts are bent at a same angle corresponding to the recessed corner, so as to be connected to each other.
According to another embodiment of the present invention, there is provided a method of fabricating a mask for optically transcribing a pattern corresponding to integrated circuits onto a semiconductor substrate, by using an exposure device. The method includes creating data sets of a plurality of features on the mask, the features corresponding to circuit elements for forming the integrated circuits; selecting first data sets of isolated edges from the data sets of the plurality of features; creating second data sets of bar-type auxiliary features in view of the selected first data sets of the isolated edges, the bar-type auxiliary features having predetermined widths and extending in parallel along isolated edges spaced from each isolated edge by a predetermined distance; creating third data sets of the bar-type auxiliary features corresponding to the recessed corner in view of the first data sets of isolated edges and the second data sets of bar-type auxiliary features; creating fourth data sets of polygonal auxiliary features by removing extension parts of the bar-type auxiliary features, which extend within the predetermined distance from the isolated edges, in view of the second data sets of bar-type auxiliary features corresponding to the recessed corner; creating final auxiliary feature data sets by replacing the third data set of the bar-type auxiliary features corresponding to the recessed corner among the second data sets of the bar-type auxiliary features with the fourth data sets of the polygonal auxiliary features; and creating mask pattern data sets by combining the data sets of the features and the final auxiliary feature data sets.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.